With the sharp development of lsi and vlsi , the integration of chip gets denser and denser . but the extra ports for testing is limited and test is more difficult than before . we even must spend more time and money on chip testing rather than chip design 大规模集成和超大规模集成电路迅速发展，使芯片的集成度越来越高，而供外部测试的引脚却很少，测试问题日趋困难，甚至使芯片测试比芯片本身的设计和生产要付出更高的代价。
As a part of the pre - research of national defense project - soc application in next generation of airplane , the work in this dissertation is to use the certain standard on - chip bus to design a system on chip ( soc ) , in which a 32 - bit embedded microprocessor is a host 作为国防十五预研项目“ soc在新一代战斗机的应用”的一部分，本课题的主要研究内容是采用标准片上总线设计一个以32位嵌入式微处理器为主处理器的片上系统( soc ) 。
It is shown that our presented circuit model was correct . secondly , on the basis of analghng the fhahon of pcd reader of contactless ic card , the softwar flow chat of cothetless ic card controller based on chip - thoing algorithin and the hardwar circuit and anenna of the reader were designed 第二，在分析非接触ic卡读写器功能的基础上，设计基于时间片算法的非接触ic卡控制器软件流程图和读写器硬件电路以及非接触ic卡读卡器的天线。
It is based on umc 0 . 6 m bcd process . a built - in power mosfet with low on - resistance and a lossless current sensing circuit on chip provide fast and precise current mode control . furthermore , the whole losses decrease and high efficiency up to 90 % can be obtained 它采用umc0 . 6 mbcd工艺制程,利用内置的低导通电阻功率mosfet和内置的无损耗电流感应电路实现了快速精确的电流模式控制,同时也降低了功耗,提高了转换效率,典型的效率可达90 % 。
In the third chapter , the principles of randomizer and de - randomizer are illuminated , and the hardware realization is also given . the fourth chapter is focused on the design of ip ( intellectual property ) and the analysis of the principle of rs encoding and decoding . based on the theory of design reuse in soc ( system on chip ) , this chapter is devoted to the design and implementation of rs decoder ip which can be implied in three hdtv channel decoder standard 第四章首先介绍了ip的基本知识和设计流程，接着对rs码的编码和译码进行详细的理论分析研究，提出rs编译码器实现方法，然后根据soc可复用设计设计思想，设计了一个应用于hdtv信道解码的rs译码ip核，最后给出dvb - crs译码器的asic设计，并给出了其规模和性能。
Two plasmids , which contain hbv specific dna fragment and hsv1 dna fragment , were amplified by solid phase two loci pcr and detected by enzymatic indicator system on a gene chip that was constructed by primer immobilization and modified with thiol group on chip surface . for building detection technology by dna chip in clinical , the virus genomes were extracted from the clinical positive samples by one - step nucleic acid extraction 采用已建立的芯片制备方法，在该六种质粒中选择含有hbv与hsv1两种病毒dna序列的质粒为模板，进行同相两重pcr ，采用芯片酶学枪测对固相两重pcr的扩增结果进行检测，得到良好的芯片酶学检测结果。
The design of cdma terminal chip is a very actual value and extensive application problem in the field of cdma technology application . with the development of micro - electronics technology , the design of integrated circuit has stepped into the age of soc ( system on chip ) , which provide a brand - new method for cdma communication system project . in this paper , a design of cdma2000 1x spread modulation soc has be researched with large scale field programmle gate array device , and make a certain results Cdma终端芯片设计是cdma技术应用领域中一个具有重要实际应用价值和广阔应用前景的研究课题。随着微电子技术的发展，集成电路设计进入了片上系统时代，这为cdma移动通信系统设计提供了一个全新的技术手段。本文将基于cdma技术，用大规模可编程逻辑器件对第三代移动通信cdma20001x的扩频调制片上系统设计做了进一步的探讨和研究，并取得了一定的成果。
With rapid developments of system on chip ( soc ) , programmable logic devices ( pld ) , including complex programmable logic device ( cpld ) and field programmable gate array ( fpga ) , can support in - system programmability ( isp ) and become more popular in the world . this requires better download cables than before , which are used to program plds 随着片上系统( soc , systemonchip )时代的到来,包括复杂可编程逻辑器件( cpld , complexprogrammablelogicdevice )和现场可编程门阵列( fpga , fieldprogrammablegatearray )的可编程逻辑器件,具有系统内可再编程的独特优点,应用越来越广泛。
Due to the development of 1c technology , now a complex system can be integrated in a chip called system on chip ( soc ) . the design of soc needs new design methodologys and modeling tools . systemc is an open c + + modeling platform promoted by the open systemc initiative , which consists of a well defined set of c + + classes and a simulation kernel , supporting design abstractions at the register - transfer , behavioral , and system levels . the advantages of systemc include the ability for hardware - software co - design , the ability to exchange ip easily and efficiently , and the ability to reuse test benches across different levels of modeling abstraction 系统级芯片的设计需要新的设计方法和建模工具。 systemc是osci ( opensystemcinitiative )组织制定和维护的一种开放源码的c + +建模平台，它由一个定义良好的c + +类库及仿真内核组成，支持对系统进行寄存器传输级，行为级和系统级的描述。 systemc的优点包括对软硬件联合设计的支持，更高效和方便的进行ip交换，以及在不同的抽象模型间复用测试基准的能力。
